1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices and, more particularly, to a structure directed to and a method for creating a de-lamination resistant interconnection bonding pad in a semiconductor device.
2. Description of the Related Art
A bonding pad connects an integrated circuit on a chip to an integrated circuit outside the chip. FIG. 1 illustrates a cross-sectional view of a conventional semiconductor memory device having a device isolation region 110, a bonding pad 350 for communicating signals externally to the chip, and a DRAM (dynamic random access memory) cell having a stack capacitor and a switching transistor 120. In FIG. 1, A1 represents a memory cell region, and A2 represents a bonding pad region. Reference numeral 120 represents a switching transistor in memory cell region A1, and reference numerals 130,140, 170 and 280 represent interlayer dielectric layers. Reference numerals 150 and 160 represent a direct contact hole and bit line, respectively. Reference numeral 210 represents a lower electrode of the stack capacitor, and reference numeral 240 represents an upper electrode of the stack capacitor. A capacitor dielectric layer (not shown) is formed between the upper and lower electrodes 210 and 240 of the stack capacitor.
In a conventional bonding pad structure as shown in FIG. 1, an intermetallic dielectric layer 310 is formed between a first aluminum interconnection layer 300 and a second aluminum interconnection layer 330, with a filled contact hole 320 providing the electrical connection between the two aluminum layers. First aluminum interconnection layer 300 is sized such that it underlies intermetallic dielectric layer 310, and when metallically bonded to second aluminum interconnection layer 330 at a later step, provides a structure that mechanically binds the three layers together at the bonding pad location to improve de-lamination characteristics.
As the size of memory device chips decrease, the size of the bonding pads also decrease. Recently, the size of a bonding pad has been reduced from about 100 μm×100 μm to 80 μm×80 μm or below in accordance with increased integration density of semiconductor memory devices. Accordingly, the contact surface area between first aluminum interconnection layer 300, which constitutes the lower structure of multilayer bonding pad 350, and fourth interlayer dielectric layer 280 decreases, and thus first aluminum interconnection layer 300 may be easily separated from fourth interlayer dielectric layer 280 at the interface therebetween.
One conventional method for overcoming such increased de-lamination characteristics provides for the forming of a polycrystalline silicon (polysilicon) pattern under a bonding pad to prevent the bonding pad from peeling during subsequent manufacturing processes. The use of a polysilicon interface between the metal bond pad and the interlayer dielectric prevents bond pad peeling or lifting by having chemically compatible interlayer surfaces, thereby providing attendant increased adhesive properties. A significant disadvantage, however, is that the polysilicon layer is typically deposited directly over a layer of insulating material rather than over a layer of a metallic material, thereby providing adhesion and anchoring characteristics that are not optimal.
Further, to eliminate the extra process steps of conventional improved bonding pad construction techniques, new techniques for forming a capacitor typically include forming a bottom capacitor plate at the same time as a bottom bonding pad and forming a top capacitor plate at the same time as a top bonding pad, with a single dielectric layer juxtaposed therebetween. While the process step elimination improves the manufacturing throughput of ICs with improved bonding pads by using only three existing deposition layers, the improved manufacturing throughput is at the expense of a more reliable bonding pad structure, specifically structural improvements that can be obtained using embedded and filled via holes discussed above to also provide a depth anchor for added de-lamination resistance.
Various approaches to such interlayer anchoring techniques provide for differing degrees of depth anchoring in addition to the complementary metal/dielectric surfaces. A significant disadvantage of such approaches is that they require many additional fabrication process steps for implementation, rather than fabricating the bonding pad anchoring structure simultaneous with other circuit element processing steps.